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CAT25010, CAT25020, CAT25040 1-Kb, 2-Kb and 4-Kb SPI Serial CMOS EEPROM
Description
The CAT25010/20/40 are 1-Kb/2-Kb/4-Kb Serial CMOS EEPROM devices internally organized as 128x8/256x8/512x8 bits. They feature a 16-byte page write buffer and support the Serial Peripheral Interface (SPI) protocol. The device is enabled through a Chip Select (CS) input. In addition, the required bus signals are a clock input (SCK), data input (SI) and data output (SO) lines. The HOLD input may be used to pause any serial communication with the CAT25010/20/40 device. These devices feature software and hardware write protection, including partial as well as full array protection.
Features
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SOIC-8 V SUFFIX CASE 751BD
MSOP-8 Z SUFFIX CASE 846AD
TDFN-8 VP2 SUFFIX CASE 511AK
* * * * * * * * * * * * *
10 MHz SPI Compatible 1.8 V to 5.5 V Supply Voltage Range SPI Modes (0,0) & (1,1) 16-byte Page Write Buffer Self-timed Write Cycle Hardware and Software Protection Block Write Protection - Protect 1/4, 1/2 or Entire EEPROM Array Low Power CMOS Technology 1,000,000 Program/Erase Cycles 100 Year Data Retention Industrial and Extended Temperature Range 8-lead PDIP, SOIC, TSSOP and 8-pad TDFN Packages These Devices are Pb-Free, Halogen Free/BFR Free, and RoHS Compliant
VCC
PDIP-8 L SUFFIX CASE 646AA
TSSOP-8 Y SUFFIX CASE 948AL
PIN CONFIGURATION
CS SO WP VSS 1 VCC HOLD SCK SI
PDIP (L), SOIC (V), MSOP (Z) TSSOP (Y), TDFN (VP2)
PIN FUNCTION
Pin Name CS SO WP Function Chip Select Serial Data Output Write Protect Ground Serial Data Input Serial Clock Hold Transmission Input Power Supply
SI CS WP HOLD SCK VSS CAT25010 CAT25020 CAT25040 SO
VSS SI SCK HOLD VCC
Figure 1. Functional Symbol
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 15 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2010
February, 2010 - Rev. 21
1
Publication Order Number: CAT25010/D
CAT25010, CAT25020, CAT25040
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters Operating Temperature Storage Temperature Voltage on any Pin with Respect to Ground (Note 1) Ratings -45 to +130 -65 to +150 -0.5 to VCC + 0.5 Units C C V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol NEND (Note 3) TDR Endurance Data Retention Parameter Min 1,000,000 100 Units Program / Erase Cycles Years
Table 3. D.C. OPERATING CHARACTERISTICS (VCC = +1.8 V to +5.5 V, TA = -40C to +125C unless otherwise specified.)
Symbol ICC ISB1 ISB2 IL ILO VIL VIH VOL1 VOH1 VOL2 VOH2 Parameter Supply Current Test Conditions Read, Write, VCC = 5.0 V, SO open VIN = GND or VCC, CS = VCC, WP = VCC, VCC = 5.0 V VIN = GND or VCC, CS = VCC, WP = GND, VCC = 5.0 V VIN = GND or VCC CS = VCC, VOUT = GND or VCC TA = -40C to +85C TA = -40C to +125C TA = -40C to +85C TA = -40C to +125C -2 -1 -1 -0.5 0.7 VCC VCC > 2.5 V, IOL = 3.0 mA VCC > 2.5 V, IOH = -1.6 mA VCC > 1.8 V, IOL = 150 mA VCC > 1.8 V, IOH = -100 mA VCC - 0.2 V VCC - 0.8 V 0.2 10 MHz / -40C to 85C 5 MHz / -40C to 125C Min Max 2 2 2 4 5 2 1 2 0.3 VCC VCC + 0.5 0.4 Units mA mA mA mA mA mA mA mA V V V V V V
Standby Current Standby Current
Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage
Table 4. PIN CAPACITANCE (Note 2) (TA = 25C, f = 1.0 MHz, VCC = +5.0 V)
Symbol COUT CIN Output Capacitance (SO) Input Capacitance (CS, SCK, SI, WP, HOLD) Test Conditions VOUT = 0 V VIN = 0 V Min Typ Max 8 8 Units pF pF
1. The DC input voltage on any pin should not be lower than -0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may undershoot to no less than -1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns. 2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. 3. Page Mode, VCC = 5 V, 25C.
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CAT25010, CAT25020, CAT25040
Table 5. A.C. CHARACTERISTICS (TA = -40C to +125C, unless otherwise specified.) (Notes 4, 8)
VCC = 2.5 V - 5.5 V VCC = 1.8 V - 5.5 V Symbol fSCK tSU tH tWH tWL tLZ tRI (Note 5) tFI (Note 5) tHD tCD tV tHO tDIS tHZ tCS tCSS tCSH tCNS tCNH tWPS tWPH tWC (Note 7) Clock Frequency Data Setup Time Data Hold Time SCK High Time SCK Low Time HOLD to Output Low Z Input Rise Time Input Fall Time HOLD Setup Time HOLD Hold Time Output Valid from Clock Low Output Hold Time Output Disable Time HOLD to Output High Z CS High Time CS Setup Time CS Hold Time CS Inactive Setup Time CS Inactive Hold Time WP Setup Time WP Hold Time Write Cycle Time 50 20 30 20 20 10 100 5 0 50 100 20 15 20 15 15 10 60 5 0 10 75 0 20 25 Parameter Min DC 40 40 75 75 50 2 2 0 10 40 Max 5 TA = -405C to +855C Min DC 20 20 40 40 25 2 2 Max 10 Units MHz ns ns ns ns ns ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns ms
Table 6. POWER-UP TIMING (Notes 5, 6)
Symbol tPUR tPUW Power-up to Read Operation Power-up to Write Operation Parameter Max 1 1 Units ms ms
4. AC Test Conditions: Input Pulse Voltages: 0.3 VCC to 0.7 VCC Input rise and fall times: 10 ns Input and output reference voltages: 0.5 VCC Output load: current source IOL max/IOH max; CL = 50 pF 5. This parameter is tested initially and after a design or process change that affects the parameter. 6. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. 7. tWC is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle. 8. All Chip Select (CS) timing parameters are defined relative to the positive clock edge (Figure 2). tCSH timing specification is valid for die revision D and higher. The die revision D is identified by letter "D" or a dedicated marking code on top of the package. For previous product revision (Rev. C) the tCSH is defined relative to the negative clock edge (please refer to data sheet Doc. No. MD-1006 Rev. U)
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CAT25010, CAT25020, CAT25040
Pin Description Functional Description
SI: The serial data input pin accepts op-codes, addresses and data. In SPI modes (0,0) and (1,1) input data is latched on the rising edge of the SCK clock input. SO: The serial data output pin is used to transfer data out of the device. In SPI modes (0,0) and (1,1) data is shifted out on the falling edge of the SCK clock. SCK: The serial clock input pin accepts the clock provided by the host and used for synchronizing communication between host and CAT25010/20/40. CS: The chip select input pin is used to enable/disable the CAT25010/20/40. When CS is high, the SO output is tri-stated (high impedance) and the device is in Standby Mode (unless an internal write operation is in progress). Every communication session between host and CAT25010/20/40 must be preceded by a high to low transition and concluded with a low to high transition of the CS input. WP: The write protect input pin will allow all write operations to the device when held high. When WP pin is tied low all write operations are inhibited. HOLD: The HOLD input pin is used to pause transmission between host and CAT25010/20/40, without having to retransmit the entire sequence at a later time. To pause, HOLD must be taken low and to resume it must be taken back high, with the SCK input low during both transitions. When not used for pausing, the HOLD input should be tied to VCC, either directly or through a resistor.
CS tCNH SCK tSU SI tH VALID IN tV tHO SO HI-Z VALID OUT tRI tFI tCSS tWH tWL
The CAT25010/20/40 devices support the Serial Peripheral Interface (SPI) bus protocol, modes (0,0) and (1,1). The device contains an 8-bit instruction register. The instruction set and associated op-codes are listed in Table 7. Reading data stored in the CAT25010/20/40 is accomplished by simply providing the READ command and an address. Writing to the CAT25010/20/40, in addition to a WRITE command, address and data, also requires enabling the device for writing by first setting certain bits in a Status Register, as will be explained later. After a high to low transition on the CS input pin, the CAT25010/20/40 will accept any one of the six instruction op-codes listed in Table 7 and will ignore all other possible 8-bit combinations. The communication protocol follows the timing from Figure 2.
Table 7. INSTRUCTION SET (Note 9)
Instruction WREN WRDI RDSR WRSR READ WRITE Opcode 0000 0110 0000 0100 0000 0101 0000 0001 0000 X011 0000 X010 Operation Enable Write Operations Disable Write Operations Read Status Register Write Status Register Read Data from Memory Write Data to Memory
9. X = 0 for CAT25010, CAT25020. X = A8 for CAT25040 tCS
tCSH
tCNS
tV
tDIS HI-Z
Figure 2. Synchronous Data Timing Status Register
The Status Register, as shown in Table 8, contains a number of status and control bits. The RDY (Ready) bit indicates whether the device is busy with a write operation. This bit is automatically set to 1 during an internal write cycle, and reset to 0 when the device is ready to accept commands. For the host, this bit is read only. The WEL (Write Enable Latch) bit is set/reset by the WREN/WRDI commands. When set to 1, the device is in a
Write Enable state and when set to 0, the device is in a Write Disable state. The BP0 and BP1 (Block Protect) bits determine which blocks are currently write protected. They are set by the user with the WRSR command and are non-volatile. The user is allowed to protect a quarter, one half or the entire memory, by setting these bits according to Table 9. The protected blocks then become read-only.
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CAT25010, CAT25020, CAT25040
Table 8. STATUS REGISTER
7 1 6 1 5 1 4 1 3 BP1 2 BP0 1 WEL 0 RDY
Table 9. BLOCK PROTECTION BITS
Status Register Bits BP1 0 0 1 1 BP0 0 1 0 1 None CAT25010: 060-07F, CAT25020: 0C0-0FF, CAT25040: 180-1FF CAT25010: 040-07F, CAT25020: 080-0FF, CAT25040: 100-1FF CAT25010: 000-07F, CAT25020: 000-0FF, CAT25040: 000-1FF Array Address Protected Protection No Protection Quarter Array Protection Half Array Protection Full Array Protection
WRITE OPERATIONS instruction to the CAT25010/20/40. Care must be taken to The CAT25010/20/40 device powers up into a write take the CS input high after the WREN instruction, as disable state. The device contains a Write Enable Latch (WEL) which must be set before attempting to write to the otherwise the Write Enable Latch will not be properly set. memory array or to the status register. In addition, the WREN timing is illustrated in Figure 3. The WREN address of the memory location(s) to be written must be instruction must be sent prior to any WRITE or WRSR outside the protected area, as defined by BP0 and BP1 bits instruction. from the status register. The internal write enable latch is reset by sending the WRDI instruction as shown in Figure 4. Disabling write Write Enable and Write Disable operations by resetting the WEL bit, will protect the device The internal Write Enable Latch and the corresponding against inadvertent writes. Status Register WEL bit are set by sending the WREN
CS
SCK
SI
0
0
0
0
0
1
1
0
SO
HIGH IMPEDANCE Dashed Line = mode (1, 1)
Figure 3. WREN Timing
CS
SCK
SI
0
0
0
0
0
1
0
0
SO
HIGH IMPEDANCE Dashed Line = mode (1, 1)
Figure 4. WRDI Timing
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CAT25010, CAT25020, CAT25040
Byte Write Page Write
Once the WEL bit is set, the user may execute a write sequence, by sending a WRITE instruction, a 8-bit address and data as shown in Figure 5. For the CAT25040, bit 3 of the write instruction opcode contains A8 address bit. Internal programming will start after the low to high CS transition. During an internal write cycle, all commands, except for RDSR (Read Status Register) will be ignored. The RDY bit will indicate if the internal write cycle is in progress (RDY high), or the device is ready to accept commands (RDY low).
After sending the first data byte to the CAT25010/20/40, the host may continue sending data, up to a total of 16 bytes, according to timing shown in Figure 6. After each data byte, the lower order address bits are automatically incremented, while the higher order address bits (page address) remain unchanged. If during this process the end of page is exceeded, then loading will "roll over" to the first byte in the page, thus possibly overwriting previously loaded data. Following completion of the write cycle, the CAT25010/20/40 is automatically returned to the write disable state.
CS 0 SCK OPCODE SI 0 0 0 0 X* 0 1 0 A7 BYTE ADDRESS DATA IN 1 2 3 4 5 6 7 8 13 14 15 16 17 18 19 20 21 22 23
A0 D7 D6 D5 D4 D3 D2 D1 D0
SO
HIGH IMPEDANCE Dashed Line = mode (1, 1) * X = 0 for CAT25010, CAT25020. x = A8 for CAT25040
Figure 5. Byte WRITE Timing
CS 0 SCK OPCODE SI 0 0 0 0 X* 0 1 0 A7 BYTEADDRESS A0 Data Data Data Byte 1 Byte 2 Byte 3 HIGH IMPEDANCE Dashed Line = mode (1, 1) * X = 0 for CAT25010, CAT25020. x = A8 for CAT25040 1 2 3 4 5 6 7 8 13 14 15 16-23 24-31 16+(N-1)x8-1..16+(N-1)x8 16+Nx8-1 DATA IN Data Byte N 7..1 0
SO
Figure 6. Page WRITE Timing
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CAT25010, CAT25020, CAT25040
Write Status Register Write Protection
The Status Register is written by sending a WRSR instruction according to timing shown in Figure 7. Only bits 2 and 3 can be written using the WRSR command.
When WP input is low all write operations to the memory array and Status Register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the Status Register. The WP input timing is shown in Figure 8.
CS 0 SCK OPCODE SI 0 0 0 0 0 0 0 1 7 MSB SO HIGH IMPEDANCE Dashed Line = mode (1, 1) 6 5 4 DATA IN 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
2
1
0
Figure 7. WRSR Timing
tWPS
tWPH
CS
SCK
WP
WP Dashed Line = mode (1, 1)
Figure 8. WP Timing
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CAT25010, CAT25020, CAT25040
READ OPERATIONS
Read from Memory Array
To read from memory, the host sends a READ instruction followed by a 8-bit address (for the CAT25040, bit 3 of the read instruction opcode contains A8 address bit). After receiving the last address bit, the CAT25010/20/40 will respond by shifting out data on the SO pin (as shown in Figure 9). Sequentially stored data can be read out by simply continuing to run the clock. The internal address pointer is automatically incremented to the next higher address as data is shifted out. After reaching the highest memory address, the address counter "rolls over" to the lowest memory
address, and the read cycle can be continued indefinitely. The read operation is terminated by taking CS high.
Read Status Register
To read the status register, the host simply sends a RDSR command. After receiving the last bit of the command, the CAT25010/20/40 will shift out the contents of the status register on the SO pin (Figure 10). The status register may be read at any time, including during an internal write cycle. While the internal write cycle is in progress, the RDSR command will output the RDY (Ready) bit status only (i.e., data out = FFh).
CS 0 SCK OPCODE SI 0 0 0 0 X* 0 1 1 A7 BYTE ADDRESS A0 DATA OUT D7 D6 D5 D4 D3 D2 D1 D0 MSB 1 2 3 4 5 6 7 8 9 12 13 14 15 16 17 18 19 20 21 22
SO
HIGH IMPEDANCE Dashed Line = mode (1, 1) * X = 0 for CAT25010, CAT25020. X = A8 for CAT25040
Figure 9. READ Timing
CS 0 SCK OPCODE SI 0 0 0 0 0 1 0 1 DATA OUT 7 MSB 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
SO
HIGH IMPEDANCE Dashed Line = mode (1, 1)
Figure 10. RDSR Timing
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CAT25010, CAT25020, CAT25040
Hold Operation
The HOLD input can be used to pause communication between host and CAT25010/20/40. To pause, HOLD must be taken low while SCK is low (Figure 11). During the hold condition the device must remain selected (CS low). During the pause, the data output pin (SO) is tri-stated (high impedance) and SI transitions are ignored. To resume communication, HOLD must be taken high while SCK is low. Design Considerations The CAT25010/20/40 devices incorporate Power-On Reset (POR) circuitry which protects the internal logic against powering up in the wrong state. The device will power up into Standby mode after VCC exceeds the POR trigger level and will power down into Reset mode when
VCC drops below the POR trigger level. This bi-directional POR behavior protects the device against `brown-out' failure following a temporary loss of power. The CAT25010/20/40 device powers up in a write disable state and in a low power standby mode. A WREN instruction must be issued prior to any writes to the device. After power up, the CS pin must be brought low to enter a ready state and receive an instruction. After a successful byte/page write or status register write, the device goes into a write disable mode. The CS input must be set high after the proper number of clock cycles to start the internal write cycle. Access to the memory array during an internal write cycle is ignored and programming is continued. Any invalid op-code will be ignored and the serial output pin (SO) will remain in the high impedance state.
CS SCK tHD HOLD
tCD
tCD
tHD tHZ
SO Dashed Line = mode (1, 1)
HIGH IMPEDANCE tLZ
Figure 11. HOLD Timing
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CAT25010, CAT25020, CAT25040
PACKAGE DIMENSIONS
PDIP-8, 300 mils CASE 646AA-01 ISSUE A
SYMBOL A A1 A2 b E1 b2 c D E E1 e eB PIN # 1 IDENTIFICATION D L 7.87 2.92 3.30 0.38 2.92 0.36 1.14 0.20 9.02 7.62 6.10 3.30 0.46 1.52 0.25 9.27 7.87 6.35 2.54 BSC 10.92 3.80 4.95 0.56 1.78 0.36 10.16 8.25 7.11 MIN NOM MAX 5.33
TOP VIEW E
A
A2
A1 b2 L c
e SIDE VIEW Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MS-001.
b
eB
END VIEW
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CAT25010, CAT25020, CAT25040
PACKAGE DIMENSIONS
SOIC 8, 150 mils CASE 751BD-01 ISSUE O
SYMBOL A A1 b c E1 E D E E1 e h L PIN # 1 IDENTIFICATION TOP VIEW 0.25 0.40 MIN 1.35 0.10 0.33 0.19 4.80 5.80 3.80 1.27 BSC 0.50 1.27 NOM MAX 1.75 0.25 0.51 0.25 5.00 6.20 4.00
0
8
D
h
A1
A
c e SIDE VIEW b L END VIEW
Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012.
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CAT25010, CAT25020, CAT25040
PACKAGE DIMENSIONS
TSSOP8, 4.4x3 CASE 948AL-01 ISSUE O
b
SYMBOL
A A1 A2 b E1 E c D E E1 e L L1
MIN
0.05 0.80 0.19 0.09 2.90 6.30 4.30
NOM
MAX
1.20 0.15
0.90
1.05 0.30 0.20
3.00 6.40 4.40 0.65 BSC 1.00 REF
3.10 6.50 4.50
0.50
0.60
0.75
e
0
8
TOP VIEW D
A2
A
q1
c
A1 SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153.
L1 END VIEW
L
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CAT25010, CAT25020, CAT25040
PACKAGE DIMENSIONS
TDFN8, 2x3 CASE 511AK-01 ISSUE A
D A e b
E
E2 PIN#1 IDENTIFICATION
A1 PIN#1 INDEX AREA D2 L
TOP VIEW
SIDE VIEW
BOTTOM VIEW
SYMBOL A A1 A2 A3 b D D2 E E2 e L
MIN 0.70 0.00 0.45 0.20 1.90 1.30 2.90 1.20 0.20
NOM 0.75 0.02 0.55 0.20 REF 0.25 2.00 1.40 3.00 1.30 0.50 TYP 0.30
MAX 0.80 0.05 0.65 0.30 2.10 1.50 3.10 1.40 0.40 FRONT VIEW A2 A3
Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MO-229.
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CAT25010, CAT25020, CAT25040
PACKAGE DIMENSIONS
MSOP 8, 3x3 CASE 846AD-01 ISSUE O
SYMBOL A A1 A2 b c E E1 D E E1 e L L1 L2 0.40 0.05 0.75 0.22 0.13 2.90 4.80 2.90 3.00 4.90 3.00 0.65 BSC 0.60 0.95 REF 0.25 BSC 0.80 0.10 0.85 MIN NOM MAX 1.10 0.15 0.95 0.38 0.23 3.10 5.00 3.10
0
6
TOP VIEW
D
A
A2
DETAIL A
A1
e SIDE VIEW
b
c END VIEW
q L2 Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-187. L L1 DETAIL A
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CAT25010, CAT25020, CAT25040
Example of Ordering Information (Note 12)
Prefix CAT Device # 25040 Suffix V I -G T3
Company ID Product Number 25010: 1-Kb 25020: 2-Kb 25040: 4-Kb
Temperature Range I = Industrial (-40C to +85C) E = Extended (-40C to +125C)
Lead Finish G: NiPdAu Blank: Matte-Tin
Tape & Reel (Note 15) T: Tape & Reel 3: 3,000 Units / Reel
Package L: PDIP V: SOIC, JEDEC Y: TSSOP VP2: TDFN (2 x 3 mm) Z: MSOP (Note 13)
10. All packages are RoHS-compliant (Lead-free, Halogen-free). 11. The standard lead finish is NiPdAu. 12. The device used in the above example is a CAT25040VI-GT3 (SOIC, Industrial Temperature, NiPdAu, Tape & Reel, 3,000/Reel). 13. For MSOP package availability, please contact your nearest ON Semiconductor Sales office. 14. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office. 15. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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CAT25010/D

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